1. Technical Field
Various exemplary aspects of the present invention relate to semiconductor apparatuses and related methods. In particular, certain exemplary aspects relate to a three-dimensional semiconductor apparatus.
2. Related Art
In order to increase the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus has been developed. The 3D semiconductor includes a package of a plurality of stacked chips. The 3D semiconductor apparatus may achieve a maximum degree of integration in the same space as a regular semiconductor by vertically stacking two or more chips.
The 3D semiconductor apparatus may be realized in a variety of ways. For example, a plurality of chips having the same structure are stacked and are connected by wires such as metal wires, and are able to operate as a single semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which silicon vias vertically pass through a plurality of stacked chips so that all the chips are connected through the silicon vias. Since the through-silicon vias vertically pass through the respective chips, in the TSV type semiconductor apparatus, the size of a package may be efficiently decreased compared to the size of a wired semiconductor apparatus.
In general, the TSV type semiconductor apparatus may be composed of a master chip and a plurality of slave chips which are electrically connected with the master chip through TSVs. For example, the master chip in a memory apparatus includes all logic circuits provided for the operation of the memory apparatus in a peripheral circuit region, and the slave chips include memory cores for data storage and circuits for the operation of the memory cores, so as to operate as a single semiconductor apparatus.
Since a plurality of chips stacked in a 3D semiconductor apparatus operate as a single semiconductor apparatus, they share data input and output. In the wired semiconductor apparatus, the data outputted from the respective stacked chips may be transferred to a controller through input/output lines. In the TSV semiconductor apparatus, the slave chip data may be transmitted to the master chip and thereby outputted through pads disposed on the master chip. In order to improve the operating speed of the semiconductor apparatus, it is necessary to output all the data from the stacked chips at the same time.
However, because the stacked chips have different characteristics due to variations in PVT (process, voltage and temperature), it is difficult for them to perform similarly. More specifically, the different PVT properties create skews between the respective chips. Thus, a skew in data output timing between a chip having a high operating speed and a chip having a low operating speed may result. In order to secure a data valid window in the existence of the skew, therefore, the operating speed of the semiconductor apparatus should be lowered, which is not desirable.